Rameen

Rameen

Digital Design & Verification | CNNs from Scratch | FPGA & Embedded Systems

Based in: Lahore, PakistanCurrently: Private Electrical Engineering Tutor, Private Electrical Engineering TutorExperience: 2 years

Hire me

A rigorous Digital Design and Verification Engineer who bridges the gap between complex algorithms and hardware implementation. From building CNNs entirely in NumPy to verifying high-throughput JPEG encoders using Cocotb and Python golden models, I specialize in ensuring functional accuracy in hardware-oriented systems. Proven track record in model-based control and FPGA deployment, with a deep interest in the intersection of AI and hardware acceleration.

Experience

Private Electrical Engineering Tutor

Private Electrical Engineering Tutorpart time2025 – Present

Summary

Provide one-on-one instruction to undergraduate Electrical Engineering students in electric circuits, digital logic, programming fundamentals, engineering mathematics, and physics. Develop individualized problem-solving strategies and technical explanations for complex engineering concepts, adapting instruction to students' backgrounds and learning needs. Mentor an undergraduate Electrical Engineering student studying in Germany, supporting their preparation in an engineering course and contributing to their achievement of Distinction.

Results

  • Mentored a student in Germany to achieve Distinction in their engineering course.
Electric CircuitsDigital LogicProgramming FundamentalsEngineering MathematicsPhysics

Digital Design Verification Intern

Maktab-e-Digital SystemsLahore, PakistanworkJun 2025 – Aug 2025

Summary

Digital Design Verification for a hardware-oriented JPEG image encoder.

What I did

  • Contributed to the development and verification of a hardware-oriented JPEG image encoder, working across color-space conversion, discrete cosine transform (DCT), quantization, and encoding stages.
  • Developed and executed SystemVerilog testbenches to evaluate module functionality and identify design errors throughout the image-processing pipeline.
  • Analyzed ModelSim simulation waveforms to trace functional discrepancies and verify expected behavior across individual processing stages.
  • Applied digital design and verification concepts to an image-processing system, gaining practical experience in hardware-oriented algorithm implementation and verification workflows.

Results

  • Verified 7+ core hardware modules (DCT, Quantization, Huffman, FIFO, Y/Cb/Cr paths) using Cocotb and Python golden models.
  • Caught and resolved functional mismatches between SystemVerilog RTL and Python reference models at the simulation stage, preventing post-synthesis errors.
  • Validated complex pipeline behaviors, including timing, data flow, and byte-stuffing handling, ensuring bit-level parity with software models.
SystemVerilogCocotbPythonModelSimJPEGDigital Design VerificationRTL DebuggingHardware/Software Co-verification

Substitute Teacher

Army Public School (APS) Boys CampusLahore, Pakistanwork2024 – 2024
Delivered lessons and maintained academic continuity across assigned classes in the absence of regular faculty. Adapted explanations and classroom activities for students with varied levels of preparation while maintaining an effective learning environment.

Skills

Technical

NumPy
PythonPython
SystemVerilog
CNNs
Logistic Regression
PID control
MATLAB/Simulink
Vivado
ModelSim/QuestaSim
FPGA development
Cocotb
SVM
Generative AI
ESP32
CC
scikit-learn

Languages

Urdu
English

Projects

Self-Balancing Robot: System Identification & Model-Based Control

Developeracademic
Developed a two-wheeled inverted-pendulum platform using an ESP32-S3 and MPU6050 IMU, implementing complementary-filter state estimation and real-time PID stabilization. Collected impulse-response data through an on-chip circular buffer and identified the plant model G(s) = b/(s2 - a), estimating physical parameters (m, h, J) in MATLAB to reproduce the observed oscillatory dynamics. Designed a lead-lag compensator from the identified model, increasing phase margin from 21.8° to 51.3° and reducing settling time by approximately 50% relative to the PID controller. Discretized the controller using the Tustin transformation and deployed it on the embedded platform, achieving approximately 60% lower steady-state oscillation than the baseline PID controller.
ESP32-S3MPU6050 IMUMATLABPID controlLead-lag compensationTustin transformation

Elevator Control System on FPGA

Designeracademic
Designed a finite-state-machine-based elevator controller in SystemVerilog, implementing floor requests, movement sequencing, and state transitions for multi-floor operation. Verified controller behavior through ModelSim simulation and synthesized the design for hardware deployment on an Artix-7 FPGA using Vivado.
SystemVerilogModelSimArtix-7 FPGAVivadoFSM
View the code

Digital System Design Labs

Designeracademic
Designed and verified combinational and sequential digital circuits in SystemVerilog, including a seven-segment display driver and RGB comparator. Simulated designs in QuestaSim and deployed selected implementations on a Nexys A7 FPGA using Vivado for hardware-level validation.
SystemVerilogQuestaSimNexys A7 FPGAVivado
View the code

Fashion-MNIST Image Classification

Developerpersonal
Investigated the structure and class separability of the Fashion-MNIST dataset using PCA projections, pixel-importance analysis, and class-similarity heatmaps to inform model selection. Implemented Logistic Regression and a convolutional neural network entirely from scratch in NumPy, including convolution, max pooling, dropout, momentum-based SGD, and backpropagation. Evaluated model performance using test accuracy and macro-F1, comparing the scratch-built CNN against an RBF-kernel SVM and Logistic Regression baseline. Achieved 92.08% test accuracy and 0.921 macro-F1 with the NumPy CNN, compared with 90.33% accuracy for SVM and 82.08% for Logistic Regression.
NumPyPCACNNLogistic RegressionSVMSGDGenerative AI (Assistant)

JPEG Image Encoder

Designerpersonal
Designed and implemented a hardware-oriented JPEG encoding pipeline covering color-space conversion, discrete cosine transform (DCT), quantization, and entropy encoding. Verified 7 core modules using Cocotb testbenches and Python golden models to ensure bit-accurate hardware implementation.
SystemVerilogCocotbPythonDigital DesignDCTImage Compression
View the code

Education

Bachelor of Science

University of Engineering and Technology (UET), LahoreElectrical Engineering2023 – May 2027

Coursework

Electric CircuitsDigital Systems DesignSignals and SystemsControl SystemsPower System AnalysisMicroprocessorsComputer ArchitectureMachine LearningElectronicsEmbedded SystemsProbability and Statistics

Intermediate

Punjab College, LahorePre-Engineering2021 – 2023

Coursework

PhysicsMathematicsChemistry

Matriculation

Jadeed Dastagir Ideal High School, LahoreScience2019 – 2021

Coursework

PhysicsMathematicsComputer Science

Recognition

Awards

PMLTC Scholarship Recipient

PMLTC2025

Awarded a full scholarship with monthly stipend in recognition of academic excellence and potential in Electrical Engineering.

Certifications

Generative AI Course

Pak Angels2025

Certificate of Substitute Teaching

Army Public School (APS) Boys Campus2024
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