Syed owais Ali shah

AI FullStack Engineer specializing in Voice AI and Scalable Backend Orchestration

Based in: Karachi, PakistanCurrently: AI FullStack Engineer, Ehsaan TechExperience: 4 years

Syed is an experienced Software Engineer with a strong background in building AI-powered voice agents, CRM workflows, and computer vision pipelines. He excels at integrating LLMs and RAG systems into full-stack applications using NestJS, FastAPI, and Next.js.

Experience

AI FullStack Engineer

Ehsaan TechworkJul 2025 – Present

Developed the backend orchestration layer for AI-powered voice agents using NestJS, TypeScript, Vapi webhooks, and MySQL, processing over 1,000 call events per day. Built pipelines to ingest and store AI-generated call summaries, outcomes, recordings, transcripts, and lead information for automated CRM workflows. Orchestrated AI-driven CRM workflows (QaulAI) via backend services, defining relational schemas and optimized SQL queries to ensure data consistency across 3+ services and reduce manual reconciliation efforts by ~40%. Integrated computer vision inference services and backend APIs to connect YOLO detections with inspection workflows. Built Python-based data ingestion and preprocessing pipelines using iCrawler, processing 10k+ images to support ML experimentation and backend feature validation.

NestJSTypeScriptVapiMySQLCRMSQLComputer VisionYOLOPythoniCrawlerML

Software Engineer

Linux FoundationworkApr 2025 – Jul 2025

Streamlined onboarding and developer experience for the RISC-V Unified Database by configuring Devcontainers and validating environments, reducing setup time by 40%.. Debugged and optimized complex RISC-V infrastructure codebases, increasing CI reliability and module-level test coverage by 30%. Designed a scope-based pretty-printer for .idl files using AST traversal; shipped as a CLI tool adopted across 3 repositories by 10+ contributors.

RISC-VDevcontainersCIAST traversalCLIC++Bash

Senior Research Intern

Micro Electronic Research LabinternshipAug 2022 – Nov 2024

Engineered simulation and implimented testing frameworks, reducing RISC-V performance analysis time by 50%. Contributed to a GEMM accelerator project, improving matrix computation throughput by ~25% for AI/ML workloads. Specified and verified a single-cycle RISC-V processor in Verilog, achieving 95% testbench coverage using Cocotb.

RISC-VGEMM acceleratorVerilogCocotbC++Bash